LVDS to TTL/CMOS level translator
19/May/2008
updated 23/May
While experimenting with the Si570 programmable DSPLL technology crystal oscillator from SiLabs I needed a level translator as the chip I got was the LVDS version (SiLabs also produces a CMOS version) and I wanted to drive a Johnson counter divide-by-4 circuit with a 74AC74 which in turn drives a QSD with a SN74CBT3253. The 3253 runs on Vcc = 5V and needs ACT family level at its inputs, the same for the 74AC74 chip (AC family stands for Advanced CMOS). But the output from the Si570 is LVDS (Low-Voltage Differential Signaling).
Fig 1 - Level Chart (http://www.interfacebus.com/voltage_interface.html)
Fig 2 - Characteristics of a LVDS signal.
The signal at each output pin of the Si570 chip is a 350 mVp-p square wave, according to its data sheet where we find 700 mVp-p swing in differential use so we take half that value for a single-ended output. This signal is centered on 1.2V, at the output pin the voltage swings 350mV above and below this mid-point voltage. We need to translate this to a signal whose mid-point voltage is around 2.5V and swing is 4 to 5 Vp-p. So we need a DC level shifting and around 22 dB of gain. There is no need for a very sharp and well defined square wave form in the level translator circuit, the 74AC74 edge-triggered flip-flop works very well with rounded-off signals. The important point is the circuit must not introduce phase noise (jitter noise, which means the zero crossing point would be randomly wandering).
There are IC's made for this purpose, I tried a FIN1002 I got from Cecil, KD5NWA but this is a 3.3V part so it does work but not optimally with the 3253 running on 5V. Input and output voltage depends on Vcc for CMOS parts. So I tried a simple transistor circuit.
Fig 3 - Level translator circuit. Q1 is a BFR92 or any low power RF
part with Ft > 1GHz. Standing collector current is 4 mA, gain is 26 dB.
. 
Fig 4 - Simulated S parameters for the level translator circuit.
Tests
I build the circuit and put it to work with a Si570 (thanks to Tom Hoflich, KM5H) oscillator build on the PCI and kit of parts from Dave, WB6DHW.
1 - I tried driving the 74AC74 through a step-up ferrite transformer, a Mini-Circuits ADT4-6T but results were poor, the 74AC74 divider stopped working around 55 MHz at the input, 13.7MHz at the output. Connecting directly worked just the same.
2 - I then connected a FIN1002 LVDS-> LVTTL (Low Voltage TTL) level translator and got the 74AC74 working up to 190 MHz/input 47 MHz/output. The 74AC74 is a part guaranteed to work up to 140 MHz minimum, 160 typical. The problem is the FIN1002 is a LVTTL output part, not exactly what the 74AC74 wants. This last one could be replaced with a LVTTL part but then the 3253 would not work well..!. Replacing the 3253 with a LVTTL part would solve this but would cause a small reduction in attainable dynamic range; In a QSD type mixer the Vcc is like a barrier, signals start clipping once a level at the output is reached.
3 - Then I experimented with the transistor circuit, first with a BF199, an old favorite with Ft = 550 MHz. From simulation I knew the transistor minimum Ft should be 1 GHz and the results agreed, I got output from the 74AC74 divider circuit up to 130 MHz/input. I then substituted a BFR92, a 5 GHz low cost part and results were very good, I got output from the 74AC74 up to 230 MHz/input even though this is way more than the typical part according to the datasheet.
Once again I remind there is a Si570 CMOS version, but to those that are interested in the lower jitter specs for the LVDS version this simple circuit might be a good option.
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23/May
I received an email from David, WB4ONA, he simulated the circuit with the aid of LT-Spice, a free SPICE program downloadable from http://www.linear.com/. He found the circuit could be improved by removing the emitter capacitor and by increasing the collector resistor to 768 ohms.
Fig 5 - On the left the original circuit, to the right the modified circuit.
Fig 6 - Green = input signal, blue = output in original circuit, red = output
in modified circuit.
We see the modified circuit does provide a better shaped square wave. The simulation frequency was set to 100 MHz.
I used PSPICE in the past but have not used it lately so I downloaded LT-Spice and took it for a spin.
After getting success running the file David sent to me, I modified the circuit a bit more to include the source impedance of the generator (50 ohms, single ended output impedance of the Si570) and also placed 5pF capacitors at the outputs to simulate a CMOS gate (74HC74 typical input capacitance).
Fig 7 - The circuits with additions.
Fig 8 - Green = input signal, blue = output in original circuit, red = output
in modified circuit.
We see a severe ringing at the input (this shouldn't pose a problem, probably comes from base and emitter internal inductances and capacitances) and the sawtooth wave at the outputs. The original circuit has a much steeper falling side while the modified one offers a nearly textbook sawtooth.
A note about these graphs: it takes a very good oscilloscope to see these waveforms as it should respond equally well to the harmonics (a 100 MHz scope just won't do it and in fact it will probably show a nearly good sine wave!).
Just for the curiosity, both about the LT-Spice software and the circuit itself, I
run FFTs of the output waveforms:
Fig 9 Fig10
We see the blue line from the original circuit with heavy content of even order harmonics, the green line from the modified circuit shows even order harmonics attenuated, resembling the original square wave (a square wave has no even order harmonics, just odd ones).
All in all I liked very much the suggestion David gave me after his (5 minute he told me) simulation exercise. Now it is time to test the real thing on the workbench, time allowing!